Very thick metal interconnection scheme in IC chips

ABSTRACT

A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.

This application claims priority to U.S. Provisional Patent ApplicationSer. No. 60/592358, filed on Jul. 29, 2004, which is herein incorporatedby reference in its entirety.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the manufacturing of high speed, low powerconsumption, low voltage, and/or high current Integrated Circuit (IC)chips, and, more specifically, to methods of creating fine lineinterconnections and coarse metal interconnections on top of the fineline interconnections for high speed, low power consumption, lowvoltage, and/or high current (IC) chips.

(2) Description of the Related Art

When the dimensions of Integrated Circuits are scaled down, the cost perdie is decreased while some aspects of performance are improved. Themetal connections which connect the Integrated Circuit to other circuitor system components become of relative more importance and have, withthe further miniaturization of the IC, an increasingly negative impacton circuit performance. The parasitic capacitance and resistance of themetal interconnections increase, which degrades the chip performancesignificantly. Of most concern in this respect is the voltage drop alongthe power and ground buses and the RC delay of the critical signalpaths. Attempts to reduce the resistance by using wider metal linesresult in higher capacitance of these wires.

Since the 1960's, sputtered aluminum has become a main stream ICinterconnection metal material. The aluminum film is sputtered coveringthe whole wafer, and then the metal is patterned using photolithographymethods and dry and/or wet etching. It is technically difficult andeconomically expensive to create thicker than 2 μm aluminum metal linesdue to the cost and stress concerns of blanket sputtering. About 1995,damascene copper metal became an alternative for IC metalinterconnection. In damascene copper, the insulator is patterned andcopper metal lines are formed within the insulator openings by blanketelectroplating copper and chemical mechanical polishing (CMP) to removethe unwanted copper. Electroplating the whole wafer with thick metalcreates large stress and carries a very high material (metal) cost.Furthermore, the thickness of damascene copper is usually defined by theinsulator thickness, typically chemical vapor deposited (CVD) oxides,which does not offer the desired thickness due to stress and costconcerns. Again it is also technically difficult and economicallyexpensive to create thicker than 2 μm copper lines.

U.S. Pat. No. 6,495,442 to M. S. Lin et al and U.S. Pat. No. 6,383,916to M. S. Lin, add, in a post passivation processing sequence, a thicklayer of dielectric over a layer of passivation and layers of wide andthick metal lines on top of the thick layer of dielectric.

SUMMARY OF THE INVENTION

It is the primary objective of the invention to provide a newinterconnection scheme especially useful for high speed, low powerconsumption, low voltage, and/or high current IC chips.

Another objective of the invention is to provide a selectiveelectroplating method for forming a thick metal, as thick as 20 microns.

It is yet another objective of the invention to provide a newinterconnection scheme comprising both coarse and fine lineinterconnection schemes in an IC chip.

A further objective of the invention is to provide a method forfabricating a coarse interconnection scheme overlying a fine lineinterconnection scheme.

A still further objective of the invention is to provide a method forfabricating a coarse interconnection scheme by an embossing process.

In accordance with the objectives of the invention, a method of formingcoarse and fine line interconnection schemes in an IC chip is achieved.A semiconductor substrate is provided. A fine line metal interconnectionstructure comprising one or more layers of metals is provided overlyingthe semiconductor substrate. A coarse metal interconnect structure isformed over the fine line metal interconnection structure by anembossing process. A passivation layer is provided overlying the coarsemetal interconnection structure.

Also in accordance with the objectives of the invention, a metalinterconnection scheme comprising both fine line and coarse metalschemes is achieved. A semiconductor substrate is provided. Fine linemetal interconnection comprising one or more layers of metals overlyingthe semiconductor substrate is provided. A coarse metal interconnectionstructure in one layer is provided and is overlying the fine line metalinterconnection; said coarse metal interconnection is further covered bya passivation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional representation of a fine lineinterconnection scheme of the prior art.

FIGS. 2-7 are cross sectional representations of a first preferredembodiment of the present invention.

FIG. 8 is a cross sectional representation of a second preferredembodiment of the present invention.

FIG. 9 is a cross sectional representation of a third preferredembodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention discloses a new IC interconnection scheme that isespecially useful for high speed, low power consumption, low voltage,and/or high current IC chips, typically formed on semiconductor wafers.The invention also discloses an embossing process, a selectiveelectroplating method to form a thick metal, as thick as 20 microns.Incorporating this embossing method, a new interconnection scheme isdescribed, comprising both coarse and fine line interconnection schemesin an IC chip. The coarse metal interconnection, typically formed byselective electroplating technology, is located on top of the fine lineinterconnection scheme. It is especially useful for long distance lines,clock, power and ground buses, and other applications such as high Qinductors and bypass lines. The fine line interconnections are moreappropriate to be used for local interconnections. The combinedstructure of coarse and fine line interconnections forms a newinterconnection scheme that not only enhances IC speed, but also lowerspower consumption.

FIG. 1 illustrates an IC chip of the prior art. As FIG. 1 depicts, theentire interconnection scheme of the IC chip is made of the fine pitchmetal wires whose typical width/thickness is less than about 2 microns.The manufacturing process of such a structure is the damascene processwhich deposits a blanket film of metal conductor on the dielectric layerwith traces formed by micro-lithography processes. The blanket film isthen subjected to a planarizing process, such as chemical mechanicalpolishing (CMP) to remove the unwanted metal material located outside ofthe traces. Only the metal body in the traces remains after the CMPprocess. Semiconductor device structures 12 are shown in and on thesemiconductor substrate 10. The device structures are covered with aninsulating layer 14. Fine line interconnections 18 are formed withindielectric layers 16. Typically, the intermetal dielectric (IMD) layers16 comprise silicon-based oxides, such as silicon dioxide formed by achemical vapor deposition (CVD) process, CVD TEOS oxide, spin-on-glass(SOG), fluorosilicate glass (FSG), high density plasma CVD oxides, or acomposite layer formed by a portion of this group of materials. The IMDlayers typically have a thickness of between about 1000 and 10,000Angstroms. Passivation layer 22 is shown with openings to top fine linemetal pads 20.

In the present invention, the embossing process to form the coarseinterconnection scheme is different from the damascene process used inthe prior art as shown above. FIGS. 2-5 show a preferred embodiment ofthe present invention. In this invention, multiple layers of metalconductor with different thickness/width form the entire ICinterconnection. Specifically, the metal layers can be divided into twosegments—top and lower metal schemes. The top metal scheme is formed bycoarse metal bodies; that is gold or copper with a thickness greaterthan about 3 microns. The lower metal scheme is formed by fine lineinterconnection; that is, copper or aluminum having a thickness of lessthan about 2 microns. Between these two interconnection schemes lies adiffusion barrier, made of, for example, oxynitride or nitride, which isdeposited to prevent the transition metal used in the coarse metalscheme from penetrating into the fine line circuitry/device area. Thethickness of the transitional metal diffusion barrier is about 400 to1000 Angstroms.

Referring now more particularly to FIG. 2, there is shown asemiconductor substrate 10. Transistors and other devices 12 are formedin and on the substrate. The surface of substrate 10 is covered by aninsulating layer 14, formed over the devices.

Layers 16 contain one or more layers of dielectric, interspersed withone or more metal interconnect lines 18 that make up a network ofelectrical connections. These metal layers are referred to as fine linemetal interconnections. Typically, the intermetal dielectric (IMD)layers comprise silicon-based oxides, such as silicon dioxide formed bya chemical vapor deposition (CVD) process, CVD TEOS oxide, spin-on-glass(SOG), fluorosilicate glass (FSG), high density plasma CVD oxides, or acomposite layer formed by a portion of this group of materials. The IMDlayers typically have a thickness of between about 1000 and 10,000Angstroms. The fine line metal interconnections are typically formed bysputtering aluminum or an aluminum alloy and patterning the aluminum toform the fine metal lines. Alternatively, the fine lines may be formedby a copper damascene process. In the copper damascene process, thecopper is protected by an adhesion/barrier layer not only underlying thecopper, but also surrounding the copper at the sidewalls of the linethrough the IMD. These fine lines typically have a thickness of lessthan about 2 microns. In the fabrication process of the fine line metalinterconnections, a typical clean room environment of class 10 or lessis required; that is, having no more than 10 particles larger than 0.5microns in any given cubic foot of air. The fine line IC metal isfabricated using 5×steppers or scanners or better and using aphotoresist layer having thickness of less than 5 microns.

Now, in a key feature of the present invention shown in FIG. 3, atransition metal diffusion barrier layer 24 is deposited over the entiresurface of the topmost IMD layer 16. The transition metal diffusionbarrier layer is formed of, for example, silicon oxynitride or siliconnitride and functions to prevent the penetration of the transition metalused in the coarse metal scheme (such as gold, copper, silver) into thefine line circuitry and device areas. The barrier layer 24 has athickness of between about 100 and 5000 Angstroms. The diffusion barrier24 forms a global diffusion layer to protect all of the underlying fineline metal circuitry and devices.

Now, the embossing process of the present invention will be described.The inventive embossing process is a selective deposition process usedto form the coarse metal interconnection scheme of the presentinvention. Referring to FIG. 4, an adhesion/diffusion barrier layer 28is deposited over the transition metal barrier layer 24. Theadhesion/diffusion barrier layer 28, preferably comprising TiW, TiN,TaN, Ti, Ta, or C, is deposited, preferably by sputtering to a thicknessof between about 100 and 5,000 Angstroms. A seed layer 30 is nextsputter deposited over the adhesion/diffusion barrier layer 28, to athickness of between about 300 and 3,000 Angstroms.

A thick photoresist is deposited over the seed layer to a thicknessgreater than the desired bulk metal thickness. Conventional lithographyis used to expose the seed layer 30 in those areas where the coarsemetal lines are to be formed, as shown by mask layer 35 in FIG. 4.

Referring now to FIG. 5, a bulk metal layer 36 is next formed byelectroplating, to a thickness of greater than about 3 μm and as thickas 20 μm, or more. The bulk metal may be gold, copper, or silver. Now,the photoresist mask is removed and the seed layer andadhesion/diffusion barrier layer not covered by the bulk metal areremoved, as shown in FIG. 6. Bulk metal 36 forms the coarse metal linesof the invention. The structure of the coarse metal lines is differentfrom the structure of the fine line metallization. An undercut 37 isformed in the adhesion/barrier layer during removal of theadhesion/barrier layer. Furthermore, there is a clear boundary betweenthe sputtered thin seed layer 30 and the electroplated thick bulk metal36. This can be seen, for example, in a transmission electron microscope(TEM) image. The boundary is due to different grain sizes and/or grainorientation in the two metal layers 30 and 36. For example, in a 1,000Angstroms thick sputtered gold layer 30 under a 4 microns thickelectroplated gold layer 36, the grain size of the sputtered gold layer30 is about 1,000 Angstroms, and the grain boundary is perpendicular tothe surface of substrate. The grain size of the electroplated gold 36 isgreater than 2 microns with the grain boundary not perpendicular, andtypically, at an angle of about 45 degrees from the substrate surface.In the fine line metal interconnections, there is no undercutting orclear boundary of grain size difference inside the aluminum or copperdamascene layer.

In more detail, the clean room environment of the coarse metal embossingprocess can be class 100 or more; that is, containing more than 100particles larger than 0.5 microns in any given cubic foot of air. Duringphotolithography in the coarse metal embossing process, aligners or1×steppers are used with a photoresist having a thickness of greaterthan about 5 microns. This contrasts with the fine line IC metal,fabricated using 5×steppers or scanners or better in a class 10environment or better and using a photoresist layer having thickness ofless than 5 microns.

A passivation layer is still needed to cover the entire interconnectionscheme so as to avoid contamination and moisture from the ambient. Thispassivation layer is more robust to resist the aggressing of variousforeign atoms, including moisture and mobile ions, from passing throughthe passivation layer. The passivation layer usually consists ofmultiple layers of materials and at least comprises a silicon nitridelayer thicker than 4000 Angstroms. More importantly, the passivationlayer is also used to prevent mechanical scratches during handling,while the transition metal diffusion barrier is only used for preventingthe penetration of gold, silver, or copper. In a first preferredembodiment of the invention, the passivation layer is deposited over thecoarse metal lines as shown in FIG. 6. The passivation layer maycomprise multiple layers and have a thickness of greater than 10,000Angstroms. For example, the passivation layer may comprise a firstinorganic dielectric layer such as an oxide layer deposited byplasma-enhanced chemical vapor deposition (PECVD) 38. Layer 39 comprisessilicon nitride. Layers 38 and 39 together comprise the passivationlayer. An opening 45 may be made through the passivation layer to makeexternal connection to the coarse metal line 36, as shown in FIG. 7.FIG. 7 also illustrates an interconnection 37 between the fine linemetal interconnections and the coarse metal lines 36.

FIG. 8 illustrates a second preferred embodiment of the presentinvention. After the passivation layer 38/39, as described above, isdeposited, a polymer layer 40 may be deposited to planarize the chipstructure. For example, the polymer may be polyimide having a thicknessin excess of 2 μm (after curing). The range of the polymer thickness canvary from 2 μm to 150 μm, dependent on electrical design requirements.For a thicker layer of polyimide, the polyimide film can be multiplecoated and cured. The polymer is formed by spin-on, printing, orlaminating. Polymer 40 may optionally be photosensitive. Examples ofother polymers that can be used include benzocyclobutene (BCB),epoxy-based material such as photoepoxy SU-8 (available from SotecMicrosystems, Renens, Switzerland), or low dielectric constant (k)materials such as parylene. The planarization process helps thephotolithographic process to open the contact pads as shown by 45 onFIG. 8.

In a third preferred embodiment of the invention, multiple dielectriclayers are deposited on the coarse metal conductor to planarize itstopography prior to the passivation layer deposition process. It may benecessary to deposit organic or inorganic dielectric layers between thecoarse metal interconnection structure and the passivation layer becausethere may be voids in the passivation layer. Any number and variety ofappropriate layers may be deposited to achieve planarization beforedepositing the passivation layer. For example, as shown in FIG. 9, aninorganic dielectric layer such as an oxide layer deposited byplasma-enhanced chemical vapor deposition (PECVD) 50 is formed over thecoarse metal lines 36. Next, a spin-on-glass layer 52 may be coated,followed by etching back of the spin-on-glass layer to conform to themorphology of the metal lines. Then, a second PE-oxide layer 54, forexample, may be deposited. A polymer layer such as parylene may bedeposited as one of the planarizing layers.

The passivation layer 56 may now be deposited on the dielectric layersthus forming a smoother morphology. The passivation layer 56 may besilicon nitride alone, or in combination with other layers as describedin the first and second embodiments. This smooth morphologycharacteristic is important to subsequent micro-lithography processeswhose depth of focus can be quite small. This characteristic is alsohelpful for the silicon nitride-based passivation layer to avoidgenerating micro-cracks around the sharp corners that might be formed bythe coarse interconnection metal body.

Sheet resistance is calculated by dividing the resistivity of the metalby the metal thickness. Sheet resistance is independent of metal linewidth and length. For example, resistivity of aluminum is 2.74micro-ohm-cm, resistivity of copper is 1.70 micro-ohm-cm, andresistivity of gold is 2.2 micro-ohm-cm. In fine line metallization, foraluminum lines having a thickness of 0.8 μm, the sheet resistance is 35milliohms per square. Damascene copper lines having a thickness of onemicron have a sheet resistance of 20 milliohms per square. In contrast,the coarse metal lines of the present invention have a metal sheetresistance of less than 7 milliohms per square. If the coarse metal lineis a 5.0 μm thick copper line, the sheet resistance is 4 milliohms persquare. If the coarse metal line is a 4.0 μm thick gold line, the sheetresistance is 5.5 milliohms per square.

In summary, the sheet resistance of the coarse metal is at least twotimes smaller than the sheet resistance of the fine line metal. As shownin the examples above, the sheet resistance of the coarse metal can befive times smaller than the sheet resistance of the fine line metal.

Although the preferred embodiment of the present invention has beenillustrated, and that form has been described in detail, it will bereadily understood by those skilled in the art that variousmodifications may be made therein without departing from the spirit ofthe invention or from the scope of the appended claims.

What is claimed is:

1. An integrated circuit chip comprising: a fine line metalinterconnection structure overlying a substrate; and a coarse metalinterconnection structure overlying said fine line metal interconnectionstructure wherein said coarse metal interconnection structure has athickness greater than 3 microns.
 2. The integrated circuit chip ofclaim 1 further comprising a diffusion barrier layer overlying said fineline metal interconnection structure and underlying said coarse metalinterconnection structure.
 3. The integrated circuit chip of claim 2wherein said diffusion barrier layer comprises silicon nitride orsilicon oxynitride.
 4. The integrated circuit chip of claim 2 whereinsaid diffusion barrier layer has a thickness of between about 100 and5000 Angstroms.
 5. The integrated circuit chip of claim 1 wherein eachlayer of said fine line metal interconnection structure comprisesaluminum or copper having a thickness of less than about 2 microns. 6.The integrated circuit chip of claim 1 wherein said coarse metalinterconnection structure comprises copper, silver, or gold.
 7. Theintegrated circuit chip of claim 6 wherein said coarse metalinterconnection structure has a thickness of up to about 20 microns. 8.The integrated circuit chip of claim 1 wherein said coarse metalinterconnection structure comprises a three layer stack, formed of anadhesion/barrier layer, a seed layer over said adhesion/barrier layer,and a bulk layer over said seed layer.
 9. The integrated circuit chip ofclaim 8 wherein said adhesion/barrier layer comprises TiW, TaN, Cr, Ti,Ta, or TiN.
 10. The integrated circuit chip of claim 8 wherein eachlayer of said fine line metal interconnection structure comprises asingle bulk layer of aluminum and wherein said coarse metalinterconnection structure comprises said seed layer and said bulk layercomprising a same metal comprising gold, silver, or copper wherein aclear boundary exists between said seed layer and said bulk layer, andwherein there is different grain size and/or orientation on the twosides of said boundary.
 11. The integrated circuit chip of claim 10wherein each layer of said fine-line metal interconnection furthercomprises an adhesion/barrier layer under said single bulk layer ofaluminum.
 12. The integrated circuit chip of claim 8 wherein each layerof said fine line metal interconnection is a layer of copper surroundedon a bottom and all sides with a fine line adhesion/barrier layerwherein said fine line adhesion/barrier layer is not undercut andwherein each layer of said coarse metal interconnection structurecomprises said three layer stack wherein said adhesion/barrier layerdoes not surround said bulk layer on its sides and wherein saidadhesion/barrier layer has an undercut under said seed layer.
 13. Theintegrated circuit chip of claim 1 further comprising a passivationlayer overlying said coarse metal interconnection structure.
 14. Theintegrated circuit chip of claim 13 wherein said passivation layercomprises one or more dielectric layers having a total thickness ofbetween about 4000 and 10,000 Angstroms and wherein said passivationlayer comprises at least a silicon nitride layer having a thickness ofgreater than about 4000 Angstroms.
 15. The integrated circuit chip ofclaim 13 further comprising a polymer layer overlying said coarse metalinterconnection structure and overlying said passivation layer.
 16. Theintegrated circuit chip of claim 15 wherein said polymer layer has athickness of between about 2 and 150 microns and wherein said polymerlayer comprises polyimide, benzocyclobutene (BCB), parylene or anepoxy-based material.
 17. The integrated circuit chip of claim 13further comprising one or more planarizing layers overlying said coarsemetal interconnection structure and underlying said passivation layer.18. The integrated circuit chip of claim 17 wherein said one or moreplanarizing layers comprise organic or inorganic dielectric layers. 19.The integrated circuit chip of claim 1 wherein a first sheet resistanceof said coarse metal interconnection structure is smaller than a secondsheet resistance of said fine line metal interconnection structure by atleast 2 times.
 20. The integrated circuit chip of claim 19 wherein saidfirst sheet resistance is smaller than 7 milliohms per square.
 21. Anintegrated circuit chip comprising: a fine line metal interconnectionstructure overlying a substrate wherein said fine line metalinterconnection structure comprises sputtered aluminum metal lines ordamascene copper metal lines; and a coarse metal interconnectionstructure overlying said fine line metal interconnection structurewherein said coarse metal interconnection structure comprises embossedmetal lines having a thickness greater than 3 microns.
 22. Theintegrated circuit chip of claim 21 further comprising a diffusionbarrier layer overlying said fine line metal interconnection structureand underlying said coarse metal interconnection structure.
 23. Theintegrated circuit chip of claim 22 wherein said diffusion barrier layercomprises silicon nitride or silicon oxynitride and has a thickness ofbetween about 100 and 5000 Angstroms.
 24. The integrated circuit chip ofclaim 21 wherein said coarse metal interconnection structure comprisescopper, silver, or gold.
 25. The integrated circuit chip of claim 21wherein said coarse metal interconnection structure has a thickness ofup to about 20 microns.
 26. The integrated circuit chip of claim 21wherein said embossed metal lines comprise a three layer stack, formedof an adhesion/barrier layer, a seed layer over said adhesion/barrierlayer, and a bulk layer over said seed layer.
 27. The integrated circuitchip of claim 26 wherein said adhesion/barrier layer comprises TiW, TaN,Cr, Ti, Ta, or TiN.
 28. The integrated circuit chip of claim 26 whereina clear boundary exists between said seed layer and said bulk layer, andwherein there is different grain size and/or orientation on the twosides of said boundary.
 29. The integrated circuit chip of claim 26wherein each layer of said fine line metal interconnection structure isa layer of copper surrounded on a bottom and all sides with a fine lineadhesion/barrier layer wherein said fine line adhesion/barrier layer isnot undercut and wherein each layer of said coarse metal interconnectionstructure comprises said three layer stack wherein said adhesion/barrierlayer does not surround said bulk layer on its sides and wherein saidadhesion/barrier layer has an undercut under said seed layer.
 30. Theintegrated circuit chip of claim 21 further comprising a passivationlayer overlying said coarse metal interconnection structure.
 31. Theintegrated circuit chip of claim 30 wherein said passivation layercomprises one or more dielectric layers having a total thickness ofbetween about 4000 and 10,000 Angstroms and wherein said passivationlayer comprises at least a topmost silicon nitride layer having athickness of greater than about 4000 Angstroms.
 32. The integratedcircuit chip of claim 30 further comprising a polymer layer overlyingsaid coarse metal interconnection structure and overlying saidpassivation layer.
 33. The integrated circuit chip of claim 32 whereinsaid polymer layer has a thickness of between about 2 and 150 micronsand wherein said polymer layer comprises polyimide, benzocyclobutene(BCB), parylene or an epoxy-based material.
 34. The integrated circuitchip of claim 30 further comprising one or more planarizing layersoverlying said coarse metal interconnection structure and underlyingsaid passivation layer.
 35. The integrated circuit chip of claim 34wherein said one or more planarizing layers comprise materials chosenfrom silicon oxide, spin-on-glass, and a polymer such as parylene. 36.The integrated circuit chip of claim 35 wherein at least one of said oneor more planarizing layers comprises spin-on-glass wherein after coatingsaid spin-on-glass layer, said spin-on-glass layer is etched back. 37.The integrated circuit chip of claim 21 wherein a first sheet resistanceof said coarse metal interconnection structure is smaller than a secondsheet resistance of said fine line metal interconnection structure by atleast 2 times.
 38. The integrated circuit chip of claim 37 wherein saidfirst sheet resistance is smaller than 7 milliohms per square.
 39. Anintegrated circuit chip comprising: a fine line metal interconnectionstructure overlying a substrate; a coarse metal interconnectionstructure overlying said fine line metal interconnection structure; anda diffusion barrier layer between said fine line metal interconnectionstructure and said coarse metal interconnection structure wherein saiddiffusion barrier layer prevents transition metals in said coarse metalinterconnection structure from reaching said fine line metalinterconnection structure.
 40. The integrated circuit chip of claim 39wherein said diffusion barrier layer comprises silicon nitride orsilicon oxynitride and has a thickness of between about 100 and 5000Angstroms.
 41. The integrated circuit chip of claim 39 wherein saidcoarse metal interconnection structure comprises copper, silver, orgold.
 42. The integrated circuit chip of claim 39 wherein said coarsemetal interconnection structure has a thickness of greater than about 3microns and up to about 20 microns.
 43. The integrated circuit chip ofclaim 39 wherein said coarse metal interconnection structure comprises athree layer stack, formed of an adhesion/barrier layer, a seed layerover said adhesion/barrier layer, and a bulk layer over said seed layer.44. The integrated circuit chip of claim 43 wherein saidadhesion/barrier layer comprises TiW, TaN, Cr, Ti, Ta, or TiN.
 45. Theintegrated circuit chip of claim 43 wherein each layer of said fine linemetal interconnection structure comprises a single bulk layer ofaluminum and wherein said coarse metal interconnection structurecomprises said seed layer and said bulk layer comprising a same metalcomprising gold, silver, or copper wherein a clear boundary existsbetween said seed layer and said bulk layer, and wherein there isdifferent grain size and/or orientation on the two sides of saidboundary.
 46. The integrated circuit chip of claim 43 wherein each layerof said fine line metal interconnection is a layer of copper surroundedon a bottom and all sides with a fine line adhesion/barrier layerwherein said fine line adhesion/barrier layer is not undercut andwherein each layer of said post-passivation metal structure comprisessaid three layer stack wherein said adhesion/barrier layer does notsurround said bulk layer on its sides and wherein said adhesion/barrierlayer has an undercut under said seed layer.
 47. The integrated circuitchip of claim 39 further comprising a passivation layer overlying saidcoarse metal interconnection structure.
 48. The integrated circuit chipof claim 47 wherein said passivation layer comprises one or moredielectric layers having a total thickness of between about 4000 and10,000 Angstroms and wherein said passivation layer comprises at least atopmost silicon nitride layer having a thickness of greater than about4000 Angstroms.
 49. The integrated circuit chip of claim 47 furthercomprising a polymer layer overlying said coarse metal interconnectionstructure and overlying said passivation layer.
 50. The integratedcircuit chip of claim 49 wherein said polymer layer has a thickness ofbetween about 2 and 150 microns and wherein said polymer layer comprisespolyimide, benzocyclobutene (BCB), parylene or an epoxy-based material.51. The integrated circuit chip of claim 47 further comprising one ormore planarizing layers overlying said coarse metal interconnectionstructure and underlying said passivation layer.
 52. The integratedcircuit chip of claim 39 wherein a first sheet resistance of said coarsemetal interconnection structure is smaller than a second sheetresistance of said fine line metal interconnection structure by at least2 times.
 53. The integrated circuit chip of claim 52 wherein said firstsheet resistance is smaller than 7 milliohms per square.
 54. A method offorming an integrated circuit chip comprising: providing a fine linemetal interconnection structure comprising one or more layers of metalsoverlying a substrate; and forming a coarse metal interconnect structureformed over said fine line metal interconnection structure by anembossing process.
 55. The method of claim 54 further comprisingproviding a diffusion barrier layer overlying said fine line metalinterconnection structure and underlying said coarse metalinterconnection structure.
 56. The method of claim 55 wherein saiddiffusion barrier layer comprises silicon nitride or silicon oxynitride.57. The method of claim 55 wherein said diffusion barrier layer has athickness of between about 100 and 5000 Angstroms.
 58. The method ofclaim 54 wherein each layer of said fine line metal interconnectionstructure comprises sputtered aluminum or damascene copper having athickness of less than about 2 microns.
 59. The method of claim 54wherein said coarse metal interconnection structure comprises copper,silver, or gold having a thickness of more than about 3 microns and upto about 20 microns.
 60. The method of claim 54 wherein said fine linemetallization structure is fabricated using 5×steppers or scanners orbetter with a photoresist thickness of less than about 5 microns andwherein said coarse metal interconnection structure is fabricated usingaligners or 1×steppers with a photoresist thickness of greater thanabout 5 microns.
 61. The method of claim 54 wherein forming said coarsemetal interconnection structure by said embossing process comprises:forming an adhesion/barrier layer; forming a seed layer over saidadhesion/barrier layer; forming a masking layer over said seed layerhaving openings where said coarse metal interconnection structure is tobe formed; selectively forming a bulk layer over said seed layer exposedwithin said openings; thereafter removing said masking layer; removingsaid seed layer not covered by said bulk layer; and removing saidadhesion/barrier layer not covered by said bulk layer.
 62. The method ofclaim 61 wherein said forming said bottom adhesion/barrier layercomprises sputtering TiW, TaN, Cr, Ti, Ta, or TiN to a thickness ofbetween about 200 and 5000 Angstroms.
 63. The method of claim 61 whereinsaid forming said seed layer comprises sputtering Au, Ag, or Cu to athickness of between about 300 and 3000 Angstroms.
 64. The method ofclaim 54 further comprising providing a passivation layer overlying saidcoarse metal interconnection structure.
 65. The method of claim 64wherein said passivation layer comprises one or more dielectric layershaving a total thickness of between about 4000 and 10,000 Angstroms andwherein said passivation layer comprises at least a topmost siliconnitride layer having a thickness of greater than about 4000 Angstroms.66. The method of claim 64 further comprising depositing a polymer layeroverlying said coarse metal interconnection structure and overlying saidpassivation layer.
 67. The method of claim 66 wherein said polymer layerhas a thickness of between about 2 and 150 microns and wherein saidpolymer layer comprises polyimide, benzocyclobutene (BCB), parylene oran epoxy-based material.
 68. The method of claim 66 wherein said polymerlayer is deposited by spin coating, by screen printing, or by laminatinga dry film of said polymer.
 69. The method of claim 64 furthercomprising providing one or more planarizing layers overlying saidcoarse metal interconnection structure and underlying said passivationlayer.
 70. The method of claim 69 wherein said one or more planarizinglayers comprise organic or inorganic dielectric layers.
 71. The methodof claim 54 wherein a first sheet resistance of said coarse metalinterconnection structure is smaller than a second sheet resistance ofsaid fine line metal interconnection structure by at least 2 times. 72.The method of claim 71 wherein said first sheet resistance is smallerthan 7 milliohms per square.